LCD Interface Options: MIPI DSI, RGB, SPI, LVDS and eDP
Eight interface families from MIPI DSI 1/2/4-lane to UART serial — matched to panel size, pin budget and host SoC. We wire, drive and document the connection, so your firmware team starts from proven register maps instead of a blank page.
The right pipe between your SoC and your pixels
The interface decides pin count, PCB width, EMI behavior and how much of your firmware budget goes to the display driver. We build modules on all eight major families and carry reference designs for common MCU and SoC pairings, so the choice is made on data — lane counts, clock rates, wire runs — not on habit.
| Interface families | MIPI DSI · RGB · SPI/QSPI · I2C · MCU · LVDS · eDP · HDMI · UART |
|---|---|
| MIPI DSI lanes | 1 / 2 / 4-lane, up to 1 Gbps per lane |
| RGB depth | 16 / 18 / 24-bit parallel |
| SPI | 3/4-wire plus QSPI, with I2C control channel |
| MCU | 8080 / 6800 modes, 8/16-bit |
| LVDS | 2/4-channel, the 7"–21.5" industrial staple |
| eDP | 1.3 / 1.4, up to 1920×1080 |
| UART | TTL / RS232 / RS485 serial screens |
| Board solutions | 1.3"–21.5" with HDMI / Android / Linux |
| Driver support | Initialization code + reference schematics |
| Lead time | Samples 7–15 days; development kits in stock |
Twelve configurations, one honest comparison
Read down the columns that matter to your design: size fit, pin budget, data rate and EMI tolerance. If your target sits between two rows, send us the SoC — we have shipped adapters and bridge boards for most pairings.
| Interface | Variants | Typical size | Pin count | Max data rate | Best fit |
|---|---|---|---|---|---|
| MIPI DSI | 1-lane | 0.96"–3.5" | 10–12 | 1 Gbps per lane | Wearables, portable devices |
| MIPI DSI | 2-lane | 2.8"–5" | 14–16 | 1 Gbps per lane | Mid-size TFT on mobile SoCs |
| MIPI DSI | 4-lane | 4.3"–8" | 20–24 | 1 Gbps per lane | 720p / 1080p high resolution |
| RGB parallel | 16 / 18 / 24-bit | 2.8"–7" | 28–50 | 25–50 MHz pixel clock | MCU / FPGA direct drive |
| SPI | 3/4-wire · QSPI | 0.96"–3.5" | 6–9 | 30–80 MHz | Low pin count, sensor HMI |
| I2C | 7/10-bit address | 0.42"–2.4" | 4 | 1 MHz | Small OLED and COG panels |
| MCU | 8080 / 6800, 8/16-bit | 2.4"–3.5" | 24–40 | 8/16-bit writes | Legacy MCU designs |
| LVDS | 2 / 4-channel | 7"–21.5" | 10–20 | 85–135 MHz per pair | Industrial HMI, long FPC runs |
| eDP | 1.3 / 1.4, 1/2-lane | 12.1"–15.6" | 10–16 | 5.4 Gbps per lane | Laptops, all-in-one panels |
| HDMI | 1.4 / 2.0 (board) | 5"–21.5" | 19-pin | 18 Gbps | Raspberry Pi, dev boards |
| UART TTL | 3.3V / 5V | 2.4"–10.1" (board) | 4–6 | 115,200–921,600 baud | Serial screens, PLC panels |
| RS232 / RS485 | Industrial serial | 4.3"–10.1" (board) | 3–9 | Up to 10 Mbps (RS485) | Factory HMI over long cable |
From host board to pixels, drawn and documented
Every interface ships with a wiring diagram like the one below: host connector, signal mapping, backlight and touch paths, and the register-init sequence for the driver IC. Hand this to your layout engineer and the display drops off your critical path — reference layouts match our standard FPC pinouts one to one, at 0.5 mm or 1.0 mm pitch.
Pick the interface by the numbers, not by habit
Four rules of thumb cover most designs. Each links to the module family where that interface does the heavy lifting.
SPI for Small Panels
0.96"–3.5" modules in 6–9 signals — SPI keeps the PCB narrow and runs to 80 MHz on ST7789V or ILI9341 drivers.
See COG ModulesMIPI DSI for Smart Displays
1/2/4-lane options carry 4.3"–8" panels to 800×1280 and beyond on a slim, EMI-friendly differential bus.
See TFT ModulesLVDS & eDP for Industrial
7"–21.5" industrial panels run over 10–20 differential signals; eDP 1.4 covers 15.6" FHD all-in-one builds.
View IndustryUART & HDMI Board Kits
Serial screens and HDMI modules from 1.3"–21.5" include the controller board — Raspberry Pi and PLC ready.
See Custom LCMInterface questions we answer every week
Short answers to the four most common interface questions. Anything else — send it with your SoC model and we reply within 48 hours.
Name your SoC. We will wire the display to it.
Send the panel size, resolution and host processor — we return an interface recommendation, a schematic snippet, pricing and a 7–15 day sample schedule, all within 48 hours, FOB Shenzhen, CIF or DDP.
